1. Field of the Invention
The present invention relates to an image coding device for compression coding of image data, and more particularly, to an image coding device for coding image data by means of an arithmetic code.
2. Description of the Related Art
As described in ISO/IEC (Committee Draft 11544, etc.), an arithmetic code is used for image encoding by adaptive prediction or the like.
An example of the construction of a coding circuit using the arithmetic code is illustrated in FIG. 1.
Binary data I of a target picture-element to be coded is input to an exclusive-OR gate 904. Binary data X.sub.0 to X.sub.n of a plurality of reference picture-elements adjacent to the target picture-element is input to a predictive-state memory 901. The predictive-state memory 901 inputs 0 or 1 as predictive picture-element data to the exclusive-OR gate 904 in accordance with the state of the reference picture-elements data. In the exclusive-OR gate 904, examination of match/mismatch between the target picture-element data I and the predictive picture-element data from the predictive-state memory 901 is conducted, and the result of the examination is output to an arithmetic coding device 903.
The arithmetic coding device 903 is provided with an interval-size register (A-register) representing a current coding-interval and a code register (C-register), both of which are shifted in accordance with the output value of the exclusive-OR gate 904. Subsequently, a consecutive 8-bit value at a specific position in the C-register is output as code data.
The contents of the predictive-state memory 901 is updated in accordance with the direction of the predictive-state memory 901 which fetches the coded result including the value of the A-register in the arithmetic coding device 903. Consequently, the predictive picture-element data is output to the exclusive-OR gate 904 from the predictive-state memory 901 adaptively to the coding operation being executed.
FIG. 2A is a flow chart showing the coding operation of the coding device 903. Let the A-register be 32 bits and the C-register also be 32 bits in the coding device 903. By definition, the interval A ranges between 0(0000H) and 0.5(8000H) and 1.0(10000H), where H represents a hexadecimal integer.
After the comparison between data of the target picture-element and data of the predictive picture-element by the exclusive-OR gate 904, a constant LSZ (least significant coding interval) is subtracted (S201) from the value A of the A-register in the arithmetic coding device 903. The constant LSZ corresponds to the occurrence probability of a less probable symbol. Subsequently, the match/mismatch between the target picture-element and the predictive picture-element is determined (S202) in the exclusive-OR gate 904. When a match occurs, re-normalization as shown in FIG. 3 is executed. On the other hand, another re-normalization as shown in FIG. 4 is executed when a mismatch occurs. The re-normalization procedure is illustrated in FIG. 2A, in which re-normalization can be executed either when a mismatch between the target picture-element data and the predictive picture-element data occurs, or when a match between the two data occurs and the value A of the A-register is less than 0.5(8000H).
As shown in FIG. 2B, to double the respective contents of the A-register and the C-register, these registers are respectively shifted to MSB by 1 bit each, and then 1 is subtracted (S301) from a CT-counter which counts the number of shifts. In this example, to treat the code data as 8-bit parallel data, the data at a specific position in the C-register is fetched as the code data whenever the C-register has shifted 8 times. Therefore, the 8-bit code data is obtained when "8" is initially set at the CT-counter; subtraction from the set value of the CT-counter is made at every 1-bit shift of the A-register; and the value of the CT-counter becomes "0."
Accordingly, a determination (S302) is made whether the value of the CT-counter is "0" or not, in which the 8-bit code data is fetched from the C-register and output (S303) the data when the value is "0"; although outputting of the code data is not executed when the value is not "0." Subsequently, it is determined (S304) whether the 1-bit shift value A of the A-register is less than 0.5 (8000H) or not. If the value A is 0.5 (8000H) or more, this re-normalization ends; and if it is less than 0.5 (8000H), the aforementioned shift operation is repeated by returning to the step S301 to execute each 1-bit shift of the A-register and the C-register and the 1-subtraction of the CT-counter. This shift operation is executed until the value of the A2O register becomes 0.5 (8000H) or more.
A description of a state transition of the A-register in the re-normalization processing will now be given in conjunction with the examples shown in FIGS. 3 and 4. When a match between the target picture-element data and the predictive picture-element data occurs, it is determined (S203) whether the value A of the A-register is less than 0.5 (8000H) or not. When the value A is 0.5 (8000H) or more, the coding operation ends through path 2 (as shown in FIG. 2A and phase 1 and phase 2 of FIG. 3). On the other hand, when the value A of the A-register is less than 0.5 (8000H), the A-register is updated (S204) by conducting a shift operation through path 1 so as to set the value A at 0.5 (8000H) or higher. The same shift operation is also executed (S205) for the C-register. Accordingly, updating of the A-register and the C-register can be executed (as shown in phase 3 of FIG. 3), in which the value of the CT-counter which counts the number of shifts of the A-register becomes "0" and consequently a high-order byte of the C-register is output as the code data.
When a mismatch occurs between the target picture-element data and the predictive picture-element data, the shift operation of the A-register will be executed until the value A of the A-register becomes 0.5 (8000H) or more (as shown in phases 1, 2, 3, and 4 in FIG. 4). As shown in FIG. 4, the shift operation of the A-register is executed three times. This shift operation accomplishes the updating (S206) of the A-register. The same shift operation is also executed (S207) for the C-register. As shown in FIG. 4, the value of the CT-counter becomes "0" at the first shift, and consequently the high-order byte of the C-register is output as code data. After the output, the value of the CT-counter is set at "8."
Accordingly, in the coding device 903, the re-normalization accompanied by the shift operation of the A-register and the C-register for the coding operation of each target picture-element is executed. The number of shifts for the re-normalization is determined by the match/mismatch between the target picture-element data and the predictive picture-element data, and by the value A of the A-register. The number of shifts is 1 when the value A is within the range of 4000H.ltoreq.A.ltoreq.7FFF, and 15 when A=0001H. Therefore, the required period for the re-normalization is not constant, which is not suitable for synchronous coding in real time with the inputting of the target picture-element to be coded.